The present invention relates to receiving data in digital systems. More specifically, the present invention relates to a receiver that receives data in digital systems using a protocol that allows data to be transmitted without using a separate clock signal.
In the art of digital signal processing, which of course includes the art of computing, it is common to transmit data from a sending block, such as a sending integrated circuit (IC) to a receiving block, such as a receiving IC. Typically, the sending block provides the data on one or more data lines, and a clock distribution network transmits a clock signal to the sending block and the receiving block on one or more clock lines. The sending block uses the clock signal to control the transitions on the data lines as data is transmitted, and the receiving block uses the clock signal to validate the received data.
As is known in the art, designing a clock distribution network is not a trivial task. Clock signal skew must be tightly controlled to ensure that the data is properly transmitted at the sending block and validated at the receiving block. Often when a block is inserted into a digital system, for example, adding an IC to a location of a printed circuit board reserved for expansion or some other type of option, the added block affects the loading of the clock distribution network differently than the loading of the data lines. This problem is addressed in U.S. Pat. No. 5,987,576 to Leith L. Johnson, et al, which is entitled xe2x80x9cMethod and Apparatus for Generating and Distributing Clock Signals with Minimal Skewxe2x80x9d, is assigned to the same assignee as the present application, and is hereby incorporated by reference.
Another area that requires considerable attention by a logic designer is transferring data from the clock domain of the sending block to the clock domain of the receiving block as data is received at the receiving block. In synchronous systems operating at the same frequency, as the distance and loading associated with the clock and data signals coupling the sending and receiving blocks vary, the phase difference between the two clock domains also varies. This problem is addressed by Paul L. Rogers in co-pending U.S. application Ser. No. 09/365,055, which was filed on Jul. 30, 1999, is entitled xe2x80x9cA Method and Apparatus for Automatically Determining the Phase Relationship Between Two Clocks Generated from the Same Sourcexe2x80x9d, and is assigned to the same assignee as the present application. This application is hereby incorporated by reference. In asynchronous systems operating at different frequencies, other techniques are used, such as handshaking or operating the receiver circuit at a frequency significantly faster than the switching frequency of the data signals.
The teachings of Rogers and Johnson et al. are cited merely to illustrate that the generation and distribution of clock signals require significant attention during the design of a digital circuit. Furthermore, clock distribution networks consume significant hardware resources, such as I/O pins on the ICs, clock buffers, and traces on the printed circuit board. Also, clock distribution networks consume considerable power because the clock signals operate at high frequencies and often drive many clock inputs. And of course, clock distribution networks do not actually carry any data.
In theory, many of the issues discussed above can be eliminated if the clock signal can be embedded in the data stream. For example, in the art of magnetic storage, hard disk drives often store data using protocols known in the art as run-length limited (RLL) codes, as taught by Wilson W. Fok in U.S. Pat. No. 4,688,016, which is entitled xe2x80x9cByte-Wide Encoder and Decoder System for RLL(1,7) Codexe2x80x9d and is hereby incorporated by reference. In the family of RLL codes, the RLL(1,7) code has gained wide acceptance. In accordance with the RLL(1,7) coding format, a sequence of unencoded binary data is converted into an encoded bit string in which each xe2x80x9c1xe2x80x9d in a coded bit sequence must be separated from the nearest adjacent xe2x80x9c1xe2x80x9d by at least one, but no more than seven xe2x80x9c0sxe2x80x9d. In this format, the most efficient coding rate results when every two unencoded data bits are converted into three coded bits. Conversely, in the decoding process, three coded data bits are converted into two decoded data bits.
Typically the clock signal is recovered from the RLL(1,7) data stream using a phase-locked loop. Often a synchronization field precedes the data field. The synchronization field provides a clock signal having hundreds or thousands of regularly spaced transitions and allows the phase-locked loop to train, or alternatively, lock on to the clock signal from the synchronization field. After the phase-locked loop is trained to the clock signal provided in the synchronization field, the RLL(1,7) data stream is provided from the data field. A phase comparator of the phase-locked loop compares transitions in the data stream with transitions in a clock signal provided by the phase-locked loop. If the transitions are not aligned, the phase comparator will issue a xe2x80x9cpump-upxe2x80x9d or xe2x80x9cpump-downxe2x80x9d signal to a voltage-controlled oscillator of the phase-locked loop to cause the clock signal provided by the phase-locked loop to remain synchronized with the data. Since RLL(1,7) code requires at least one, but no more than seven xe2x80x9c0sxe2x80x9d between xe2x80x9c1sxe2x80x9d, the phase-locked loop is guaranteed to have a data stream transition to compare with the clock signal at least once every seven clock signals.
Another protocol that embeds a clock signal in a data stream is disclosed by Peter A. Franaszek et al. in U.S. Pat. No. 4,486,739, which is entitled xe2x80x9cByte Oriented DC Balanced (0,4) 8B/10B Partitioned Block Transmission Codexe2x80x9d and is hereby incorporated by reference. The protocol disclosed by Franaszek et al. is an RLL(0,4) code, which ensures a transition at least every four clock cycles, and encodes 8 bits into 10 bits, thereby providing a coding efficiency of 80%.
Similar to the RLL(1,7) code discussed above, the protocol disclosed by Franaszek et al. typically requires a phase-locked loop to recover the clock signal from the data signal. Phase-locked loops tend to be relatively complex circuits, and are often implemented using analog circuitry. Furthermore, phase-locked loops can require hundreds or thousands of clock cycles to train onto a signal. For many types of errors, the phase-locked loop must retrain onto the signal. Also phase-locked loops can drift between clock and data edge comparisons. This drifting can be visualized as a variable skew that limits the ultimate data transfer rate. What is needed in the art is a self-clocking protocol that includes a clock signal, such as the protocol disclosed by Franaszek et al. and the RLL(1,7) code discussed above, without requiring a phase-locked loop to recover the clock signal from the data stream.
The present invention is a method and apparatus for receiving data using a self-clocking link protocol which allows data to be received without the use of a separate clock signal and without requiring a phase-locked loop to recover a clock signal from the data signal. The present invention may advantageously be used in any application where data is transmitted from one digital block to another.
A protocol for use with a receiver in accordance with the present invention is implemented using m-out-of-n encodings, with restricted transitions allowed between the encodings. By restricting the transitions, the receiver of the present invention ensures that a transition edge is present on at least two data lines carrying the protocol for every data transmission. This property allows received data to be recovered without requiring a phase-locked loop. In addition, if desired it is also possible to recover a clock signal from the received data.
As is known in the art, an m-out-of-n encoding is a binary code with a width of n bits, with exactly m bits of these n bits having a value of xe2x80x9c1xe2x80x9d and the other n-m bits having a value of xe2x80x9c0xe2x80x9d. There are n!/[m!(n-m)!] encodings possible in an m-out-of-n encoding.
The restricted transition 2-out-of-4 encoding used by the receiver of the present invention provides a self-clocking link protocol capable of receiving two bits every transition. The restricted 2-out-of-4 encoding uses 4 signals and two of the bits in each encoding must have a value of xe2x80x9c1xe2x80x9d, thereby providing a total of six encodings.
The encodings can be assigned the meanings xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d, xe2x80x9c2xe2x80x9d, xe2x80x9c3xe2x80x9d, xe2x80x9crepeatxe2x80x9d, and xe2x80x9cinvertxe2x80x9d. The allowed transitions are restricted such that the next encoding cannot be the same encoding and cannot be the inverse encoding. This restriction provides the restricted transition 2-out-of-4 encoding of the present invention with a self-clocking feature because exactly two signals change with every transition between encodings.
Each encoding has four possible allowed transitions, thereby allowing two bits of data to be transmitted every encoding transition. Whenever the xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d, xe2x80x9c2xe2x80x9d, and xe2x80x9c3xe2x80x9d encodings are transferred, the corresponding values of xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d, xe2x80x9c2xe2x80x9d, and xe2x80x9c3xe2x80x9d, respectively, result when the encodings are decoded. After transferring one of xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d, xe2x80x9c2xe2x80x9d, or xe2x80x9c3xe2x80x9d encodings, assume that the next value to be transferred is the same value. Since there is no allowed transition to the encoding representing the same value, the xe2x80x9crepeatxe2x80x9d encoding is transferred. Similarly, if the next value to be transferred is the complement value, the xe2x80x9cinvertxe2x80x9d encoding is transferred.
A receiver in accordance with the present invention includes a link differential receiver, a link receiver detector, a link receiver clock recovery unit, a link receiver valid data extender, and a link receiver decoder. Incoming data is received via a transfer medium by the link differential receiver.
The link differential receiver determines which of the six encodings are present on the input signals, and asserts exactly one of six separate encoding signals corresponding to that encoding. The encoding signals are in turn provided to the link receiver detector. The link receiver detector includes a series of flip-flops and stores information derived from the current encoding and previous encodings. The detector produces 30 detector signals, which are labeled to correspond with each possible transition from one encoding to another, including the prohibited transition to the complement value, but excluding the prohibited transition back to the same value.
The 30 detector signals are provided to the link receiver clock recovery unit and the link receiver valid data extender. The link receiver clock recovery unit receives the detector signals and recovers a clock signal from the transitions in the detector signals. The clock signal is provided to the link receiver decoder and to other circuits in the receiving block.
The link receiver valid data extender also receives the detector signals and generates extended encoding signals, which remain xe2x80x9c1xe2x80x9d for one additional encoding transition, thereby simplifying the task of decoding the values from the encodings. Accordingly, at any instant in time two of the extended encoding signals are asserted as xe2x80x9c1xe2x80x9d and the others are deasserted as xe2x80x9c0xe2x80x9d.
The extended and non-extended encoding signals are provided to the link receiver decoder, which in turn produces the decoded data at a pair of data lines. The decoded data is than transmitted to other circuits in the receiver block. Note that these other circuits may use a separate clock to receive the decoded data, or may use the clock provided by the link receiver clock recovery unit.
The present invention provides many advantages over the prior art. For example, a design implementing the present invention can have a simplified clocking distribution network because separate clock signals are not required to transmit data between blocks. In addition, phase-locked loops are not required to extract the clock signal from the data stream. Also, the present invention provides higher transfer rates than many prior art techniques.